For the regulator to operate efficiently, there must be a minimum of switching losses which requires a very fast rise time for the current. This current can only be provided by CIN, and that
Loss comparisons with different voltage regulation methods under different switching frequencies have been presented in Thus, a coordinated control method of power loss reduction and capacitor voltage balancing for AC voltage boosted FBSM-MMC has been proposed. Under the given MMC system parameters and power factor angles, the control
Coordinated control of power loss and capacitor voltage ripple reduction for AC voltage boosted FBSM MMC with second harmonic circulating current injection Authors : Muchao Xiang, Jiabing Hu 0000-0002-3670-3029 [email protected]
Request PDF | On Sep 1, 2016, Shambhu Sau and others published Analysis and reduction of capacitor ripple current in modular multilevel converter for variable speed drives | Find, read and cite
Abstract: The major drawback of Modular Multilevel Converter (MMC) based variable speed drives is that the capacitor voltage ripple varies inversely with the output frequency. This voltage ripple can be reduced at lower operating frequency by injecting circulating current into its each arm. However, this circulating current increases the overall current rating of the converter.
In , , the use of variable dc bus voltage is proposed to reduce the capacitor voltage ripple for variable speed drives. Reduction of dc bus voltage at lower output 978-1-5090-5157-1/17/$31.00 ©2017 IEEE 1451
A new control technique known as inverted error deviation (IED) control is incorporated into the main DC-link capacitor voltage regulation algorithm of a three-level neutral-point diode clamped (NPC) inverter-based
The experimental results on a 400-W three-phase half-bridge microinverter prototype validate the theoretical analysis of the dc-link capacitor optimization and show that a significant reduction of the dc-link capacitor requirement can be achieved. The proposed high-accuracy dc-link voltage controller is also implemented on this prototype to demonstrate very
Engineers note: Capacitors are key to voltage regulator design Literature Number: SNOA842. Technology Edge Republished with permission by Planet Analog Engineers note: Capacitors are key to voltage regulator design By Chester Simpson, Member of Technical Staff, Power Supply Design Group Some 99 percent of the "design" problems associated with linear and switching
This in turn leads to a further reduction of the voltage at the node and so on. If the duration of the disturbance is too long, the mechanical shaft torque of the machines gets higher than the electrical torque thus making it impossible to recover rated speed . The voltage instability then occurs in form of a progressive gradual fall of the voltage at the respective node . A
From the given experimental results, the A-VSVPWM strategy can actively control the NP voltage in the full MI and PF range and effectively reduce capacitor ripple. The
Capacitors are made within a given tolerance. The IEEE standard allows reactive power to range between 100% and 110% when applied at rated sinusoidal voltage and frequency (at 25°C case and internal temperature)
It shows that voltage regulation of the full-bridge submodules requires special provisions for energy-flow control between the converter''s main power stage and the external ac network. Novel control and hardware methods
In this paper, a novel flexible capacitor voltage control strategy for MMC as motor drives was proposed, with which the arm capacitor voltage was controlled flexibly
In order to extend the stable load range and suppress cross regulation of SIDO buck converter in continuous conduction mode (CCM), a novel ripple control technique, called as capacitor current and capacitor voltage ripple (CCVR) control, is proposed in this article.
Choose ceramic capacitors with a voltage rating of at least 1.5 times the maximum-input voltage. If tantalum capacitors are selected, they should be chosen with a voltage rating of at least twice the maximum-input voltage. A
Due to the load-to-voltage dependence of custom loads, CVR can maintain the voltage magnitude across the network at a lower level, thus reducing load demand and power losses. In the 1980s, field tests by American Electric Power (AEP) show that a 0.5% to 0.8% reduction in load demand was achieved by the voltage reduction of 1% .
Shunt capacitors reduce the induced current in the electrical circuit. Reducing the line current reduces the IR and IX voltage drops and improves the system voltage level from the capacitor
Based on the analysis, a simple but effective capacitor voltage regulation strategy and an operation parameter optimization method are proposed. Within the identified stable operation
Abstract: This paper presents and comprehensively compares various regulation control design techniques targeted to improve output voltage ripple, droop against load transients, and power
The voltage drop that can be calculated from the above Equation is the basis for the application of the capacitors. After using capacitors, the system increases the voltage due to improving the power factor and reducing the effective line current. Therefore, the voltage due to and IXL is reduced.
Even though choosing larger capacitors can smooth the NP voltage fluctuations, this will adversely reduce the power density of the motor drive [9, 10]. In addition, suppressing common mode voltage (CMV) is important for the powertrain system, as it can cause damage to the insulation of the motor [11, 12].
After using capacitors, the system increases the voltage due to improving the power factor and reducing the effective line current. Therefore, the voltage due to and IXL is reduced. The approximate percentage of voltage increase along the line can be calculated as.
From the given experimental results, the A-VSVPWM strategy can actively control the NP voltage in the full MI and PF range and effectively reduce capacitor ripple. The proposed method is more advantageous in terms of capacitor ripple, NP voltage response speed and CMV compared to the existing VSVPWM methods.
Voltage deviations from the nominal value were significantly reduced. There was a notable reduction in active power losses (I2R losses) throughout the distribution lines. The optimized capacitor placement minimized the current flow, thereby reducing resistive losses.
The placement of capacitors resulted in improved voltage levels across the distribution network. Voltage deviations from the nominal value were significantly reduced. There was a notable reduction in active power losses (I2R losses) throughout the distribution lines.
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